A high speed Reed-Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm

In this paper, a high speed Reed-Solomon (RS) decoder chip for optical communications is presented. It mainly contains one (255,239) RS decoder with 4K-bit embedded memory. Due to the operation speed limitation in I/O pad, a Delay Lock Loop (DLL) circuit is also included to generate internal high-speed clock. The RS decoder features a high speed and area-efficient key equation solver using a novel inversionless decomposed architecture for Euclidean algorithm. The test chip is implemented by 0.35µm CMOS SPQM standard cells with chip area of 2.61mm × 2.62mm. The RS decoder has the gate count of 12.4K. Test results show the proposed chip can support 2.35-Gbps data rate while operating at 294MHz with the supply voltage of 3.3V.