A clock tuning circuit for system-on-chip

Clock distribution in System-on-Chip (SoC) designs has become a problem for integrating IP cores into a single synchronous SoC, because of different clock delays in the IP cores. We propose an on-chip clock tuning circuit. Programmable delays are inserted in the clock distribution network, facilitating clock alignment and synchronization. Design iterations are eliminated, saving design effort and cost. The method also compensates for unbalanced clock trees. The circuit was implemented in a commercial chip, and demonstrated good functionality and high productivity.