Domino logic with dynamic body biased keeper

A dynamic body biased keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce contention current without sacrificing noise immunity. The proposed circuit technique is applied to wide fan-in domino OR gates. With the proposed dynamic body biased keeper circuit technique, circuit evaluation speed is increased by up to 66% while reducing power dissipation by 43% as compared to standard domino logic circuits.