A 5.9mW 6.5GMACS CID/DRAM array processor

The pattern recognition processor performs digital vector matrix multiplication using internally analog fine-grain parallel computing. The three-transistor CID/DRAM unit cell combines single-bit dynamic storage, binary multiplication, and zero-latency analog accumulation. Delta-sigma analog-to-digital conversion of the analog array outputs is combined with oversampled unary coding of the digital inputs. The 256 × 128 CID/DRAM processor with integrated 128 delta-sigma ADCs measures 3mm × 3mm in 0.5 µm CMOS and delivers 1.1 GMACS/mW.