Comparison of programmable FIR filter architectures for low power

Several implementation approaches for programmable Finite Impulse Response digital filters are compared for silicon area and power dissipation. The designs include a fully programmable MAC-based filter processor, and dedicated architectures where the filter coefficients can either be stored in registers or are fixed before synthesis. The key question is whether chip area or power can be saved by designing an optimized core processor, as compared to synthesized implementations with a straightforward mapping between the signal flow graph and the architecture.