Design considerations and experimental verification of a self oscillating line driver in .35 µm CMOS

In this paper a theoretical model for the design of high efficient SOPA power amplifiers is deducted. Switching type power amplifiers do not suffer the efficiency decay with the crest factor compared with linear type amplifiers. Using the describing function analysis, an analytical model has been derived to cope with the hard non-linear specifications of a switching type amplifier. This speeds up the design time for a high linearity, high bandwidth SOPA line driver. A CMOS implementation is used to verify the obtained insights. The designed line driver is processed in a .35µm CMOS technology. The line driver can handle ADSL signals with an MTPR over 55 dB and VDSL downstream signals with a 8.6 MHz bandwidth. The power consumption of the complete chip is 213mW for a 100mW output power.