A 1.35Gbps decision feedback equalizing receiver for the SSTL SDRAM interface with 2X oversampling phase detector for skew compensation between clock and data

A 1.35Gbps CMOS DFE (decision feedback equalization) receiver with a clock-data skew compensation was implemented for the SSTL SDRAM interface. The receiver consists of a DFE input buffer and a 2X over-sampling phase detector inside a phase synthesizer loop. Measurements of this receiver showed the increase of both time margin and voltage margin by about 20% at the data rate of 1.2Gbps compared to the case without equalization. Active chip area and power consumption are 300X1000 µm²and 275mW respectively including output drivers with a 2.5V, 0.25µm CMOS process.