Phase noise improvement of deep submicron low-voltage VCO

A low-voltage wideband 3.0-5.0 GHz complementary VCO was designed and fabricated in an 0.13 µm SOI CMOS process [1]. Non-minimum gate length was used for NMOS to improve the phase noise by exploiting waveform symmetry, maximizing output swing and reducing transistor flicker noise without any penalty to VCO performance. A phase noise improvement of up to 8 dB was observed experimentally. At 1 V VDDand 3.0 GHz, the phase noise is - 122.5 dBc/Hz at 1MHz offset, and the power dissipation is 2.5mW.