A high-performance master chip for logic circuits

A 149-component logic master chip with three levels of metallization is described. The chip can be interconnected into an array of current switch logic (CSL). The CSL gates are designed to operate at one of 2 power levels in order to minimize the overall power dissipation. The high-power CSL gate (80 mw) is used to drive gates external to the chip; the low power CSL gate (50 mw) is used to drive gates internal to the chip. Functional wirability of the master chip is demonstrated by making four different part numbers containing 3 to 12 circuits per chip. The master chip is 60 × 60 mils square, contains 24 IO pads, 83 transistors, 50 resistors, and 16 RC stabilization networks. There are three levels of metallization interspaced by rf sputtered SiO2. Two levels of wiring are used for logic and the third is used for power dissipation. The propagation delay of a 3-input CSL gate is in the 1 ns range. The transistor used in the master chip has a 0.2 mil emitter width, a 0.1 mil emitter opening for electric contact, and a 2 0.1 mil base contact. The collector junction depth of the transistor is 1.1 µ and the physical base width is 0.3 µ The ftof the transistor is 1 GHz at a collector current of 10 mA. The monte carlo transistor design techniques was applied in order to obtain the diffusion parameters which give maximum device yield. The capacitor in the RC stabilization network is made from n-p junctions. A junction capacitance of 1.5 pF/mils²was obtained.