Some factors influencing 1/F noise in silicon planar transistors

1/ noise in n-p-n silicon planar transistors is shown to have two sources. One of these sources is associated with the recombination centres that determine low-current hFEand are situated where the emitter-base depletion region meets the silicon-silicon-dioxide interface. The same relationship between hFEand 1/ noise is established for, (1) batches of production transistors with suitable processing, (2) devices in which the gain and 1/ are changed as a result of biasing a gate electrode over the emitter base oxide, and (3) devices in which the gain and 1/ noise have been changed as a result of emitter-base avalanche stressing.