Steady-state analysis of field effect transistors via the finite element method

Steady-state transport in a semiconductor is simulated for two spatial dimensions using the finite element method. The resulting algorithm is used to model IGFET´s. The model is in agreement with experimental data for the variation of threshold voltage with drain and substrate bias in devices with channel lengths varying to less than the diffused junction depth. Also modeled is the effect of non-uniform electronic charge in the insulator on device characteristics. These characteristics are similar to those measured for devices exhibiting hot-carrier instability.