Abstract :
A new MOS dynamic Ram cell utilizing a merged surface charge transistor[1] structure is described. The merged charge memory (MCM) cell uses a polysilicon electrode as both the bit sense line and one plate of each of the storage capacitors. The MCM structure is self-aligned, contactless and free of closely spaced pn junctions. Its spatial density approaches the conceptual limit of the intersection formed by two orthogonal lines of 4 W2, where W is the line width. An 8 × 8 MCM array has been fabricated, and test results as well as ASTAP[2] simulation, based on the charge control circuit model, have validated this new cell concept. Implications for chip design constraints are discussed. Advantages and limitations are highlighted where appropriate.