High performance ECL gates made by SEL method

A new process utilizing self-aligned etching and lift-off (SEL) techniques has been developed to fabricate high performance bipolar integrated circuits. The feature of the SEL is to use a polyimide film both for side etching and life-off of metal films, in order to achieve very fine lines (e. g. with 1µm width or spacing) with conventional photolithographic techniques. Integrated ECL gates have been fabricated both with conventional and SEL techiques and compared over wide ranges of power dissipation and /or speed. In the integrated circuits were employed dielectrically isolated, arsenic diffused transistors with fTof 2.0 to 2. 5 GHz. At the gate consisting of devices with 1µm emitter stripe, stage delays of about 0.4ns and power-delay products of about 1pJ were observed. It was also confirmed that the SEL technique is effective to reduce metal line spacings and to minimize parasitic capacitances.