DocumentCode
440187
Title
Schemes of clock recovery and synchronization in HDTV decoder SoC
Author
Zhang, Chunrong ; Zheng, Shibao ; Wang, Feng ; Wang, Tao
Author_Institution
Inst. of Image Commun. & Inf. Process., Shanghai Jiao Tong Univ., China
fYear
2005
fDate
28-30 May 2005
Firstpage
312
Lastpage
315
Abstract
In this paper, we present some design schemes of system clock recovery and synchronization in HDTV decoder SoC. First, a model of system clock recovery is introduced. Based on this model, an optimized hardware implementation is proposed. And then the scheme of synchronization about presentation and decoding is discussed. In the end, a solution to ensure decoding in abnormal conditions is explained.
Keywords
decoding; high definition television; synchronisation; system-on-chip; video coding; HDTV decoder SoC; clock recovery; decoding; hardware implementation; synchronization; Clocks; Counting circuits; Decoding; Delay effects; Design optimization; Digital TV; HDTV; Hardware; Pulse width modulation; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on
Print_ISBN
0-7803-9005-9
Type
conf
DOI
10.1109/IWVDVT.2005.1504613
Filename
1504613
Link To Document