DocumentCode
440191
Title
Hardware implementation of FAST-based reinforcement learning algorithm
Author
Hwang, Kao-Shing ; Hsu, Yuan-Pao ; Hsieh, His-Wen ; Lin, Hsin-Yi
Author_Institution
Dept. of Electr., Nat. Chung-Cheng Univ., Taiwan
fYear
2005
fDate
28-30 May 2005
Firstpage
435
Lastpage
438
Abstract
A FAST-based (flexible adaptable-size topology) reinforcement learning chip is implemented in this article. Basically, the FAST is an ART-like (adaptive resonance theory) mechanism. The ART is characterized as one of unsupervised learning neural network models, facilitated to solve stability-plasticity dilemma. The chip is a self organizing architecture that consists of three main structures including similarity, learning, and pruning. Dynamically adjusting the size of sensitivity regions of each neuron and adaptively pruning one of the neurons when an input pattern activates more than one neuron, the chip can preserve hardware resources (available neurons) to accommodate more categories. The clustered result by the implemented chip is then sent to an AHC (adaptive heuristic critic) architecture (emulated by a personal computer) to learn to balance an inverted pendulum system, which is also emulated by the personal computer for verifying the implemented architecture.
Keywords
field programmable gate arrays; learning (artificial intelligence); microcomputers; neural net architecture; pendulums; self-adjusting systems; adaptive heuristic critic architecture; adaptive resonance theory; flexible adaptable-size topology; hardware implementation; inverted pendulum system; reinforcement learning algorithm; self organizing architecture; Computer architecture; Hardware; Microcomputers; Network topology; Neural networks; Neurons; Resonance; Stability; Subspace constraints; Unsupervised learning;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design and Video Technology, 2005. Proceedings of 2005 IEEE International Workshop on
Print_ISBN
0-7803-9005-9
Type
conf
DOI
10.1109/IWVDVT.2005.1504643
Filename
1504643
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