DocumentCode :
44292
Title :
3-D graphics processor unit with cost-effective rasterization using valid screen space region
Author :
Lai, Yu-Kun ; Chung, Yeh-Ching
Author_Institution :
Dept. of the Electr. Eng., Nat. Chung Hsing Univ., Taichung, Taiwan
Volume :
59
Issue :
3
fYear :
2013
fDate :
Aug-13
Firstpage :
705
Lastpage :
713
Abstract :
In order to render 3-D graphics efficiently, rasterization techniques have been developed. Traditional clipping techniques using six-planes of view volume are complicated and not cost-effective. This paper develops a novel cost-effective strategy for primitives with regard to clipping in rasterization. Throughout the process, no expensive clipping action is required and no extra clipping-derived polygons are produced. It also presents the architecture of a 200-MHz multicore, multi-thread 3-D graphics SoC in 65nm 1P9M process with a core size of 4.97mm2 and 153.3mW for power consumption. The proposed clip-less architecture in rasterization processes the valid screen space region of each primitive in eight cycles, with a gate-count of only 20k. In addition, the throughput can achieve up to 25 M Triangles/Sec.
Keywords :
graphics processing units; rendering (computer graphics); system-on-chip; 3-D graphics render; 3D graphics processor unit; clipping action; clipping-derived polygons; cost-effective rasterization; frequency 200 MHz; multicore multithread 3D graphics SoC; power 153.3 mW; size 65 nm; system-on-chip; valid screen space region; Equations; Extrapolation; Hardware; Pipelines; Transforms; Visualization; 3-D graphics processor; rasterization;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/TCE.2013.6626259
Filename :
6626259
Link To Document :
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