Developing a strategic error source based design evaluation for ADC´s

In this work, we develop the foundation of an error source based design evaluation and apply it to the example of a successive-approximation-register (SAR) analog-to-digital converter (ADC). The proposed approach identifies the error sources in the design and relates them to the performance characteristics measured for prototype samples. Based on this identification, we extract the sources of dominant performance degradation and suggest a redesign to counter act the latter.