Towards a unified top-down design flow for fully differential logic blocks with improved speed and noise immunity

A new top-down design flow (RTL-to-GDSII) is proposed for achieving high-performance and noise-immune designs consisting of differential logic blocks. The differential building blocks are based on the current-mode logic (CML), which offers true differentiality with low-swing signalling, switching-independent constant power dissipation and very high-speed operation. The goal of this flow is to allow effective cancellation of inductive and capacitive noise in high-speed on-chip interconnect lines using a simple generic interconnect architecture.