Title :
Design and optimization of CMOS prescaler
Author :
Lei, Yu ; Koukab, Adil ; Declercq, Michel
Author_Institution :
Lab. d´´Electronique Gen., Ecole Polytechnique Federale de Lausanne, Switzerland
Abstract :
UWB prescaler operating from 1 GHz to 25 GHz while drawing about 3.5mA from 1.8 V power supply has been designed in 0.18 CMOS process. The prescaler features a new balanced dynamic load technique and an asymmetrical latch structure. The speed enhancement mainly comes from the asymmetrical setting of the D-latch cell, while balanced dynamic load significantly widens the frequency range and at the same time reduces power consumption. The factors and tradeoffs that govern the circuit performances are addressed to optimize the design.
Keywords :
CMOS logic circuits; circuit optimisation; integrated circuit design; prescalers; 0.18 micron; 1 to 25 GHz; 1.8 V; 3.5 mA; CMOS prescaler; CMOS process; D-latch cell; UWB prescaler; asymmetrical latch structure; balanced dynamic load technique; CMOS process; Circuit topology; Design optimization; Energy consumption; Frequency; Latches; Logic design; MOSFETs; Power supplies; Transistors;
Conference_Titel :
Research in Microelectronics and Electronics, 2005 PhD
Print_ISBN :
0-7803-9345-7
DOI :
10.1109/RME.2005.1543021
