• DocumentCode
    443267
  • Title

    Hierarchical FPGA clustering to improve routability

  • Author

    Marrakchi, Zied ; Mrabet, Hayder ; Mehrez, Habib

  • Author_Institution
    LIP6-ASIM Lab., Univ. Paris 6, France
  • Volume
    1
  • fYear
    2005
  • fDate
    25-28 July 2005
  • Firstpage
    165
  • Abstract
    In this paper we present a new clustering technique, based on the multilevel partitioning, for hierarchical FPGAs. The purpose of this technique is to reduce area and power by considering routability in early steps of the CAD flow. We show that this technique can reduce the needed tracks in the routing step by 15% compared with the other packing tools.
  • Keywords
    field programmable gate arrays; logic CAD; logic partitioning; CAD flow; field programmable gate arrays; hierarchical FPGA clustering; multilevel partitioning; Clustering algorithms; Field programmable gate arrays; Integrated circuit interconnections; Logic circuits; Logic devices; Pins; Reconfigurable logic; Routing; Switches; Table lookup;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Research in Microelectronics and Electronics, 2005 PhD
  • Print_ISBN
    0-7803-9345-7
  • Type

    conf

  • DOI
    10.1109/RME.2005.1543029
  • Filename
    1543029
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=443267