Title :
Efficient VLSI implementation of multiplication in GF(2n)
Author :
Golofit, Krzysztof
Author_Institution :
Fac. of Electron. & Inf. Technol., Warsaw Univesity of Technol., Poland
Abstract :
The paper focuses on the possibilities of hardware implementation (above all VLSI proposals) of the multiplication in GF(2n). Encouraging solutions were implemented in technology 0.35 μm and served as the models for the projection of the main circuits parameters (silicon area, speed, power consumption) for currently used and more advanced technologies.
Keywords :
VLSI; digital arithmetic; logic design; multiplying circuits; 0.35 micron; GF(2n) multiplication; VLSI implementation; hardware implementation; Circuits; Energy consumption; Equations; Galois fields; Hardware; Information technology; Paper technology; Proposals; Silicon; Very large scale integration;
Conference_Titel :
Research in Microelectronics and Electronics, 2005 PhD
Print_ISBN :
0-7803-9345-7
DOI :
10.1109/RME.2005.1543032
