Algorithmic/architectural design for H.264/MPEG-4 AVC low-power video codec

With reference to the new H.264/AVC video codec standard, this paper presents novel algorithmic and architectural solutions for the implementation of context-aware coprocessors in real-time, low-power embedded systems. The focus is on the motion estimation task which is the traditional bottleneck of video coding systems in terms of computational and memory costs. When implementing the proposed VLSI architecture in CMOS technology the same performance of the conventional full-search approach is achieved for a wide range of bit-rates, while remarkably reducing computational burden and power consumption.