DocumentCode
443924
Title
Data retention analysis on individual cells of 256Mb DRAM i n 110nm technology
Author
Weber, A. ; Birner, A. ; Krautschneider, W.
Author_Institution
Infineon, Dresden, Germany
fYear
2005
fDate
12-16 Sept. 2005
Firstpage
185
Lastpage
188
Abstract
In DRAM, every memory cell experiences an individual mixture of leakage currents which consume part of the stored charge and lead to a wide distribution of data retention time (tRet). This distribution consists of an intrinsic (main) and an extrinsic (tail) branch. The formalism of activation energies (Ea) provides information about the mechanisms involved. Activation energies of single cells in a 256M DDR memory chip and their dependence on negative gate bias (VNWLL) as well as body bias (VBB) have been investigated intensively for the first time. The worst tail cells - all within a small retention time interval - show a twofold and wide distribution of activation energies. The lower Ea distribution can be altered with VNWLL, whereas the higher Ea distribution only alters with VBB. Going from tail towards main distribution, the percentage of cells belonging to the low Ea part continuously decreases and finally disappears. We therefore conclude that a gate induced mechanism (GIDL) is the main component responsible for DRAM retention tail.
Keywords
DRAM chips; leakage currents; 110 nm; 256 Mbit; DDR memory chip; DRAM cells; DRAM retention tail; activation energies; body bias; data retention analysis; gate induced mechanism; leakage currents; negative gate bias; worst tail cells; Data analysis; Dielectrics; Electronic mail; Leakage current; Log-normal distribution; Probability distribution; Production; Random access memory; Tail; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European
Print_ISBN
0-7803-9203-5
Type
conf
DOI
10.1109/ESSDER.2005.1546616
Filename
1546616
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