CMOS integration of solid phase epitaxy for sub-50nm devices

Author

Pouydebasque, A. ; Dumont, B. ; El-Farhane, R. ; Halimaoui, A. ; Laviron, C. ; Lenoble, D. ; Rossato, C. ; Casanova, N. ; Carron, V. ; Pokrant, S. ; Skotnicki, T.

Author_Institution

Philips Semicond., Crolles, France

fYear

2005

fDate

12-16 Sept. 2005

Firstpage

419

Lastpage

422

Abstract

In this work, we report a study of the integration of NMOS and PMOS junctions with solid phase epitaxy (SPE). For the first time, considerably improved short channel effects are demonstrated with SPE for both NMOS and PMOS (-30% / -25% in DIBL at L_g=40nm for N and P devices respectively). However, a 12/15% (NMOS/PMOS) Ion degradation is observed at V_d=0.9V that is explained by a contact resistance issue. Solving this contact resistance problem enables to recover the performance of spike annealed devices within 5%. Gate capacitance measurements demonstrate no significant poly-depletion degradation. Finally no degradation is reported for the poly-edge linear junction leakage and bulk-to-drain leakage. These results demonstrate the potentiality of SPE at the 45nm node and below.

Keywords

CMOS integrated circuits; MOSFET; contact resistance; p-n junctions; solid phase epitaxial growth; 0.9 V; CMOS; NMOS junctions; PMOS junctions; contact resistance; ion degradation; poly-edge linear junction leakage; short channel effects; solid phase epitaxy; spike annealed devices; Annealing; CMOS process; CMOS technology; Contact resistance; Degradation; Epitaxial growth; Lamps; MOS devices; Solids; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference, 2005. ESSDERC 2005. Proceedings of 35th European

Print_ISBN

0-7803-9203-5

Type

conf

DOI

10.1109/ESSDER.2005.1546674

Filename

1546674