Title :
A novel storage scheme for parallel turbo decoder
Author :
He, Xiang ; Luo, Hanwen ; Zhang, Haibin
fDate :
25-28 Sept., 2005
Keywords :
Buffer storage; Clocks; Field programmable gate arrays; Graph theory; Hardware; Interleaved codes; Iterative decoding; Random access memory; Read-write memory; Throughput;
Conference_Titel :
Vehicular Technology Conference, 2005. VTC-2005-Fall. 2005 IEEE 62nd
Print_ISBN :
0-7803-9152-7
DOI :
10.1109/VETECF.2005.1558448