DocumentCode
446681
Title
Design of FGMOS log-domain filters
Author
Rodríguez-Villegas, E. ; Yufera, Alberto ; Rueda, Adoración
Author_Institution
Dept. of Electr. & Electron. Eng., Imperial Coll., London
Volume
1
fYear
2003
fDate
30-30 Dec. 2003
Firstpage
109
Abstract
In this paper, design trade-offs for a CMOS implementation of low voltage low power logarithmic filters based on floating-gate-MOS transistors (FGMOS) are analysed. Limits for power consumption, power supply and cutoff frequency of a second order filter based on log-domain integrator architecture are found. The influence of capacitor matching in FGMOS structures on the nonlinear performance of the filter is investigated
Keywords
CMOS integrated circuits; MOSFET; active filters; integrated circuit design; low-power electronics; nonlinear network analysis; CMOS implementation; FGMOS log-domain filters; FGMOS structures; capacitor matching; floating-gate-MOS transistors; log-domain integrator architecture; logarithmic filters; second order filter; Capacitance; Capacitors; Circuits; Differential equations; Energy consumption; Nonlinear filters; Power engineering and energy; Power filters; Power supplies; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Conference_Location
Cairo
ISSN
1548-3746
Print_ISBN
0-7803-8294-3
Type
conf
DOI
10.1109/MWSCAS.2003.1562230
Filename
1562230
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