Towards low-power synthesis: a common sub-expression extraction algorithm under delay constraints

This paper presents a common sub-expression extraction algorithm targeting the reduction of power consumption of multi-level combinational logic networks under delay constraints. The proposed algorithm has been prototyped and simulated using ORCAD 9.2^reg . The results show that adding delay constraints prevents the combinational logic network from suffering uncontrollable degradation in performance during the optimization process for reducing power consumption