A time and area efficient hardware implementation of the MISTY1 block cipher

A time and area efficient hardware implementation of the 64-bit NESSIE proposal, MISTY1 block cipher, is presented in this paper. The new proposed architecture achieves high-speed and small silicon area. The VLSI implementation uses feedback logic and inner pipeline with negative edge-triggered register. So, the critical path is shorter, without increasing the latency of cipher execution. Comparing with an implementation without negative edge-triggered register, about 97 % performance improvement is achieved. The proposed implementation reaches a data throughput value equal to 561 Mbps at 79 MHz clock frequency. In addition, is area efficient because only one round of the cipher is used. The design was coded using VHDL language and for the hardware implementation FPGA device was used. A detailed analysis, in terms of performance, and covered area is shown