A novel coarse grain reconfigurable processing element architecture

This paper proposes a coarse grain reconfigurable processing element (PE) for future telecommunication equipment. The authors described the first release of the simple processing element architecture that is capable to basic arithmetic operations such as addition, subtraction, multiplication, division, square and square root with same hardware (HW) processing element. It also can provide base of 2 logarithms. The proposed architecture guarantees predefined throughput and clock frequency for all these arithmetic operations