Title :
Design and verification of mixed-signal I/O IPs: an 12C bus controller
Author :
Romain, O. ; Cuénin, T. ; Garda, P.
Author_Institution :
Lab. des Instrum. et Syst. d´´Ile-de-France, Univ. Pierre et Marie Curie, Paris, France
Abstract :
The external communications between a system on a chip and its environment require mixed-signal intellectual properties such as bus or wireless interfaces. Their behaviour respects the bus protocol, in time, in packet length, in access mode. We describe in this paper firstly the design of an intellectual property (IP) modelling the interface controller for an inter-integrated controller channel (12C) bus in a mixed language (systemC and VHDL-AMS) and secondly, the real behaviour of this IP from a test bench on a hardware/software platform.
Keywords :
controllers; system buses; system-on-chip; 12C bus controller; VHDL-AMS; bus protocol; hardware-software platform; interface controller; interintegrated controller channel; mixed language; mixed-signal I/O IP; mixed-signal intellectual properties; system on a chip; systemC; wireless interfaces; Access protocols; Communication system control; Instruments; Intellectual property; Intelligent sensors; Object oriented modeling; Performance evaluation; System testing; System-on-a-chip; Universal Serial Bus;
Conference_Titel :
Industrial Electronics, 2004 IEEE International Symposium on
Print_ISBN :
0-7803-8304-4
DOI :
10.1109/ISIE.2004.1571785
