Design slope constraint for reducing noise generation and coupling mechanisms in mixed signal IC´s

Digital signal slope incidences on coupling mechanisms and noise generation in mixed-signal integrated circuits are developed and illustrated by some SPICE simulations. The minimum transition concept on some signals should allow us to reduce the noise generated by the digital part of a system on chip. Some noise measurements on silicon, caused by single inverters, confirm that reducing the slope of digital edge can decrease significantly the perturbing crosstalk in a mixed analog-digital integrated circuit. A digital design method is exposed and used to create a small block, which has the typical behaviour of used existing IPs. Comparative SPICE simulations, between a classical implemented block and a special one with well-fitted transitions, show that a noise reduction is easily obtained by increasing several transition times of digital signals without decreasing the device speed. For larger circuit, a step called ´recovery´, would be included in the design implementation flow, in order to decrease some too fast transitions.