PLL modeling method for integration in an IF receiver ASIC

The architecture of an IF wireless receiver is presented. This component is designed using standard CMOS 0.35 μm process with 3.3 V power supply and is included in professional mobile radio-communications (PMR) applications. The method employed to verify its behavior is based on models written in VHDL-AMS language. A particular point highlighted in this article is the use of Verilog-A to find out the PLL phase noise and include it to a VHDL-AMS model. Evaluating PLL phase noise is not possible with transistor level simulations due to computing time. Results obtained with our Verilog-A model are inserted in the VHDL-AMS model. The purpose of utilizing those two languages is to take advantage of features needed to test our component. The VHDL-AMS allows simulating mixed signal transient behavior with VHDL digital modules with various simulators. The Verilog-A helps computing specific block phase noise properties using RF simulators such as Cadence Spectre-RF or mentor graphics Eldo-RF. Simulation results obtained with models are in good agreement with transistor level simulations and measurement results.