• DocumentCode
    449315
  • Title

    Hardware-based precise time synchronization on Gb/s Ethernet

  • Author

    Yamada, Yoshiaki ; Ohta, Satoru ; Uematsu, Hitoshi

  • Author_Institution
    NTT Network Innovation Lab., NTT Corp., Yokosuka, Japan
  • Volume
    1
  • fYear
    2005
  • fDate
    28 Nov.-2 Dec. 2005
  • Abstract
    The accuracy and precision of time synchronization in Ethernet must be enhanced since Ethernet is becoming a critical component of telecommunication networks. This paper investigates a precise time synchronization technique that supports Gb/s Ethernet. To obtain accurate time synchronization, delay variation in message transfer and processing must be minimized. For this purpose, the paper first describes an implementation of preemptive priority queuing, which decreases the message delay variation of Ethernet. The paper then proposes a time synchronization method that is performed in the lower protocol layer and then describes its implementation on FPGA-based hardware. The proposed method achieves superior time accuracy and precision through the low message transfer/processing delay variation provided by preemptive priority, lower layer execution, and hardware implementation. The effectiveness of the method is confirmed through experiments.
  • Keywords
    field programmable gate arrays; local area networks; protocols; synchronisation; Ethernet; FPGA-based hardware; delay variation; hardware-based precise time synchronization; message transfer; protocol layer; Clocks; Delay effects; Electronic mail; Ethernet networks; Hardware; Jitter; Laboratories; Protocols; Synchronization; Technological innovation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Global Telecommunications Conference, 2005. GLOBECOM '05. IEEE
  • Print_ISBN
    0-7803-9414-3
  • Type

    conf

  • DOI
    10.1109/GLOCOM.2005.1577371
  • Filename
    1577371