Reducing the implementation complexity of combined input and output queued switches by using extended maximal matching algorithm

For a combined input and output queued (CIOQ) switch, maximal matching (MM) algorithm with a speedup of 2 has been known to deliver 100% throughput under any admissible traffic, where in each time slot, two independent schedulings and two cell transferrings are made respectively. This paper proposes a new kind of extended maximal matching (EMM) algorithm, which just utilizes a little information of VOQ length. We show that the implementation complexity of CIOQ switches is reduced by using the EMM(2) algorithm, where only one scheduling and two cell transferrings (data speedup of 2) are necessary in each time slot to achieve 100% throughput when input traffic is admissible. The EMM(2) algorithm can be easily realized by modifying the existing MM algorithms. In this paper, we provide a practical instance of EMM(2) algorithm, named EiSLIP(1,2), based on the well-known iSLIP algorithm. Simulations show that EiSLIP(1,2) algorithm with a data speedup of 2 achieves almost the same delay performance as output queued policy under uniform and non-uniform traffic with Bernoulli arrival, as well as the bursty traffic.