Optimizing the Design of a Configurable Digital Signal Processor for Accelerated Execution of the 2-D Discrete Cosine Transform

The advance of mobile electronics technology has produced handheld appliances allowing both wireless voice and data communications. As data communications become increasingly important in mobile computing applications, traditional microprocessors and the accompanying software are increasingly less able to meet the size constraints of these applications while delivering increased performance. One of the most important operations in the realm of digital signal and image processing is the 2-D Discrete Cosine Transform, used to compress both still images and streaming video. The BISON Configurable Digital Signal Processor(BCDSP) architecture detailed here uses multiple memories, few instructions, and a special pipelined floating point arithmetic function core to run on a commercially available Field Programmable Gate Array(FPGA) board. The results demonstrate that although the clock speed of the FPGA board was 2 orders of magnitude slower than the microprocessor used in this study, the BCDSP implementation was still significantly faster.