DocumentCode :
450159
Title :
Programmable LDPC decoder based on the bubble-sort algorithm
Author :
Singhal, Rohit ; Choi, Gwan ; Mahapatra, Rabi N.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
fYear :
2006
fDate :
3-7 Jan. 2006
Abstract :
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardware implementation. Due to this property, a lot of research has been done to find their suitability in different communication media. These codes have been shown to achieve near Shannon-limit performance in wireless AWGN channels. At the same time these codes can result in significant power reduction in on-chip global and semi-global interconnects. These different applications demand a variety of LDPC coder decoder structures. This paper presents a programmable design for a parallel implementation of an LDPC decoder. The programmability implies that this decoder can adapt itself to any arbitrary LDPC code for a variety of applications. This paper also presents two example configurations, with a throughput of 2.28 Gbps and 4.37 Gbps respectively.
Keywords :
decoding; error correction codes; parallel architectures; parity check codes; 2.28 Gbit/s; 4.37 Gbit/s; LDPC codes; Shannon-limit performance; bubble-sort algorithm; error correcting codes; low density parity check codes; on-chip global interconnects; power reduction; programmable LDPC decoder; semi-global interconnects; wireless AWGN channels; Computer science; Costs; Decoding; Delay; Error correction; Hardware; Parity check codes; Protection; Throughput; Turbo codes;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on
ISSN :
1063-9667
Print_ISBN :
0-7695-2502-4
Type :
conf
DOI :
10.1109/VLSID.2006.137
Filename :
1581454
Link To Document :
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