Title :
The Standard Transistor Array (STAR) Part I-A Two-Layer Metal Semicustom Design System
Author :
Gould, John M. ; Edge, Teddy M.
Author_Institution :
Electronics and Control Laboratory, Marshall Space Flight Center, AL
Abstract :
The Standard Transistor Array (STAR) design system is a two-layer metal semicustom approach to generating random logic MOS digital circuits. The STAR design system is a part of the Large Scale Microelectronics Computer-Aided Design and Test (CADAT) system [1]. The STAR design automated system includes a STAR-PLACE automatic placement program, a STAR-COMPILE compiling program, a STAR-ROUTE automatic routing program, a STAR-PRINT display program, and the ARTWORK-MANART artwork generation program. The basic STAR array, array technologies, STAR logic cell design, STAR application software, and example STAR circuit layouts are discussed in this paper.
Keywords :
Circuit testing; Design automation; Digital circuits; Large-scale systems; Logic arrays; Logic circuits; Logic design; MOSFETs; Microelectronics; Programmable logic arrays;
Conference_Titel :
Design Automation, 1980. 17th Conference on
Print_ISBN :
0-89791-020-6
DOI :
10.1109/DAC.1980.1585236
