The Design and Implementation of Fault Insertion Capabilities for ISPS

Fault tolerance is an important attribute of most computer systems, and to be effective it must be an explicit objective from the beginning of the design process. Inserting faults into a simulation of the machine and observing its behavior is a thorough and economical technique for evaluating prospective fault detection, diagnosis, recovery, and repair mechanisms. As systems become larger due to rising semiconductor integration, the expense of these fault simulations increasingly necessitates that they be performed at higher levels of abstraction (such as the register transfer level) rather than lower (such as the gate level). This can achieve major cost savings without significantly compromising fault coverage. This paper describes the design and implementation of a high level fault insertion mechanism for the Instruction Set Processor Specification (ISPS) simulator. The ISPS simulator was chosen because it is an interactive, high level simulator which is capable, mature, and widely used and accepted. The faults which can be simulated include hard and transient, deterministic and probabilistic, stuck-at and bridged, data, control, and operation types. These facilities have been implemented and demonstrated to be sound in both concept and implementation. They have been incorporated as a standard feature in the latest release of the ISPS simulator.