DocumentCode
450444
Title
A Multiple Delay Simulator for MOS LSI Circuits
Author
Nham, H.N. ; Bose, A.K.
Author_Institution
Bell Laboratories, Murray Hill, NJ
fYear
1980
fDate
23-25 June 1980
Firstpage
610
Lastpage
617
Abstract
This paper describes a multiple delay simulator for MOS LSI circuits. The basic primitives for this simulator are MOS transistor structures where the transistors are evaluated logically. Integer rise and fall delays are associated with each transition and these delays are computed automatically based on device characteristics and circuit capacitances. The simulator has been extensively used for the design verification of production LSI chips.
Keywords
Analytical models; Circuit simulation; Computational modeling; Costs; Delay; Large scale integration; Logic devices; MOSFETs; Permission; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1980. 17th Conference on
Print_ISBN
0-89791-020-6
Type
conf
DOI
10.1109/DAC.1980.1585310
Filename
1585310
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