DocumentCode

450449

Title

A United Approach to Simulation and Timing Verification at the Functional Level

Author

Mokkarala, Vighneswara Row ; Fan, Antony ; Apte, Ravi

Author_Institution

Hewlett Packard Co., Cupertino, CA

fYear

1985

fDate

23-26 June 1985

Firstpage

757

Lastpage

761

Keywords

Analytical models; Computational modeling; Delay; Design automation; Logic circuits; Logic design; Logic gates; Switches; Switching circuits; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 1985. 22nd Conference on

ISSN

0738-100X

Print_ISBN

0-8186-0635-5

Type

conf

DOI

10.1109/DAC.1985.1586030

Filename

1586030