Delay Optimization of Combinational Static CMOS Logic

Several methods for increasing the speed of combinational static CMOS circuits, including techniques for partitioning gates on the basis of circuit complexity and input arrival time, are described. The target layout style is standard cell, rather than a PLA or gate matrix scheme. Use of a standard-cell-like image allows a two-level buffered hierarchy to be introduced which is beneficial to reducing circuit delays. Preliminary results from device sizing algorithms are also given. The device sizer employs a fast, accurate, waveform-simulation-based, table-driven delay calculator to determine gate delays. A summary of results shows that partitioning techniques yield delay reductions of 10-15% compared with another currently employed program. The sizing heuristics provide an additional 15-20% increase in circuit speed.