Fast, Small, and Static Combinatorial CMOS Circuits

We present ALPS, a new way to generate layout from boolean equations. We use an original tree-structured representation of arbitrary boolean expressions, more compact than classic disjunctive form, allowing fast symbolic manipulation and natural mapping onto silicon. This implementation of ALPS produces static CMOS layout using a cascode-switch style. We present measurements done on fabricated circuits. For a large class of functions, particularly semi-regular control logic, VLSI layout generated by ALPS compares favorably in speed and area to PLAS and Standard-Cell designs.