DocumentCode
450521
Title
TRIP: An Automated Technology Mapping System
Author
Suzuki, Shigenobu ; Bitoh, Tatsushige ; Kakimoto, Masao ; Takahashi, Kazutoshi ; Sugimoto, Takao
Author_Institution
NEC CORPORATION, TOKYO, JAPAN
fYear
1987
fDate
28-1 June 1987
Firstpage
523
Lastpage
529
Abstract
A technology mapping system, used for computer design in NEC, is presented. The features of this system are technology conversion and logical/physical optimization, based on a rule base, partitioning support, conversion verification and special layout consideration. This system is practically used for many applications for technology mapping, including redesigning an existing total unit into a new unit, based on up-to-date LSI technology. The resulting effect is quick inputting of integrated circuit technology progress into practical computer design area.
Keywords
CMOS logic circuits; CMOS technology; Circuit synthesis; Design methodology; Integrated circuit technology; Large scale integration; Logic design; National electric code; Permission; Printed circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1987. 24th Conference on
ISSN
0738-100X
Print_ISBN
0-8186-0781-5
Type
conf
DOI
10.1109/DAC.1987.203292
Filename
1586276
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