Improving a PLA Area by Pull-Up Transistor Folding

The constraints limiting multiple PLA folding are the positions of pull-up transistors (Tpu) and the layout architecture which supports only I/O folding. In this paper, we present a novel architecture supporting multiple I/O, term, and pull-up foldings with through-the-cell net routing. The pull-up folding allows implementation of multiple level Boolean functions. Our architecture model achieves a better densities in comparison with PLA model.