DocumentCode
450606
Title
The Layout Synthesizer: An Automatic Netlist-to-Layout System
Author
Chen, Chao C. ; Chow, Shau-Lim
Author_Institution
Cadence Design Systems, Inc., San Jose, CA
fYear
1989
fDate
25-29 June 1989
Firstpage
232
Lastpage
238
Abstract
A system generating compacted physical layouts from MOS transistor netlists has been developed. It uses a novel graph-theoretical placement algorithm to simultaneously maximize diffusion sharing and minimize the wiring area. The algorithm is not limited to circuits that have equal numbers of NMOS and PMOS transistors. A special-purpose router using either one-layer or two-layer metal is described. Experimental results for area efficiency and run-time performance are very promising.
Keywords
CMOS logic circuits; Chaos; Layout; Logic design; Logic gates; MOSFETs; Permission; Rivers; Synthesizers; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1989. 26th Conference on
ISSN
0738-100X
Print_ISBN
0-89791-310-8
Type
conf
DOI
10.1109/DAC.1989.203401
Filename
1586385
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