Automatic Tub Region Generation for Symbolic Layout Compaction

This paper describes a new algorithm that automatically generates tub regions for VLSI symbolic layouts with quality comparable to that of human designers. The algorithm supports an explicit modeling of enclosure rules in the layout compaction task with the benefit of robustness and reduced output database size. In addition, the algorithm runs at O(n²) time and O(n) space with the expected run time of O(n log n).