DocumentCode :
450627
Title :
A Deterministic Approach to Adjacency Testing for Delay Faults
Author :
Glover, C.T. ; Mercer, M. Ray
Author_Institution :
Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX
fYear :
1989
fDate :
25-29 June 1989
Firstpage :
351
Lastpage :
356
Abstract :
Adjacency testing for delay faults is examined in both theory and implementation. We shall show that the necessary and sufficient conditions for adjacency testability yield an efficient method of robust delay test generation. Empirical results (including several different cost measurements) are presented which demonstrate that our technique: (1) achieves high fault coverages under both the robust and nonrobust delay fault models and (2) is cost effective.
Keywords :
Circuit faults; Circuit testing; Costs; Delay effects; Fault detection; Hazards; Latches; Logic testing; Propagation delay; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1989. 26th Conference on
ISSN :
0738-100X
Print_ISBN :
0-89791-310-8
Type :
conf
DOI :
10.1109/DAC.1989.203422
Filename :
1586406
Link To Document :
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