Path-Delay Constrained Floorplanning: A Mathematical Programming Approach for Initial Placement

A procedure for path-delay constrained initial placement during chip floorplanning is presented which directly incorporates timing and geometrical constraints into the process. The problem is modeled and mathematically formulated as a constrained non-linear programming problem which is systematically divided and solved in three steps: timing minimization with module overlap, module separation and timing minimization without module overlap. To save computation time, two techniques for eliminating non-logical and noncritical paths are used to reduce the number of paths considered during the optimization. Experimental results show that the placement results satisfy all given timing and geometrical constraints, and have good total normalized wire delays.