DocumentCode
450640
Title
An Automatic Test Generation Algorithm for Hardware Description Languages
Author
Norrod, Forrest E.
Author_Institution
Hewlett Packard, Fort Collins, CO
fYear
1989
fDate
25-29 June 1989
Firstpage
429
Lastpage
434
Abstract
A new approach to test generation from Hardware Description Language circuit models has been developed and implemented. The described E-algorithm generates tests for control, operation, and data faults in sequential and combinational logic modeled at the functional level. A symbolic variable notation is introduced to permit systematic fault propagation through control structures. Results of the implementation are given for a set of test cases and the application of the algorithm to a semi-custom ASIC are discussed.
Keywords
Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Computational efficiency; Hardware design languages; Logic testing; Permission; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 1989. 26th Conference on
ISSN
0738-100X
Print_ISBN
0-89791-310-8
Type
conf
DOI
10.1109/DAC.1989.203436
Filename
1586420
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