Worst-Case Delay Estimation of Transistor Groups

This paper presents two algorithms for performing worst-case delay estimation using transistor-level timing simulation techniques. The first algorithm, Dynamic Path Selection (DPS), determines in linear time the slowest paths in series-parallel transistor groups; the exponential complexity remains for transistor groups with bridges. The second algorithm, Delay Subnetwork Enumeration (DSE), complements the DPS method by taking into account logic dependencies within transistor groups. The two methods are combined in the static timing analyzer TAMIA, to provide accurate worst-case delay estimation of digital CMOS circuits.